1. Field of the Invention
This invention relates to a semiconductor memory device and, more particularly, it relates to a word line control circuit of a dynamic memory (DRAM).
2. Description of the Related Art
FIG. 7 shows a schematic block diagram of a typical conventional DRAM. Since such a block diagram is very popular and well known to those who are interested in the related field of technology, it will not be described here any further. Referring to FIG. 7, each of the memory cells (DRAM cells) MC arranged to form a matrix in the memory cell array 60 has a single transistor/single capacitor arrangement comprising a transistor Q for data transfer and a capacitor C for data hold connected in series as illustrated in FIG. 8. The transistor Q is typically a N-channel insulated gate field effect transistor (NMOS transistor) having its drain and gate respectively connected to a bit line BL and a word line WL.
For writing data into or reading data out of a selected memory cell MC, a word line drive voltage having a voltage level higher than that of the power source voltage Vcc of the DRAM by at least the threshold voltage of the transistor Q is applied to the word line WL to obtain an electric charge sufficient to carry out an operation of reading data from or writing data into the capacitor C.
A typical data writing/reading operation of the DRAM of FIG. 7 will be described by referring to FIG. 9. In the following description, the expression "internal node" of a memory cell refers to the node connecting a transistor Q and a capacitor C in a memory cell having a single transistor/single capacitor arrangement as illustrated in FIG. 8. When accessing a memory cell MC, as a row address strobe signal RAS externally supplied to the RAS input circuit 61 goes to the active level ("L"), all the row-related circuits start operating. Under this condition, the row decoder 67 selects a word line WL designated by the signal obtained by decoding the row address signal from the row address buffer circuit 62. The selected word line WL is activated as a word line driving stepped-up voltage (stepped-up voltage of the power source voltage) is supplied thereto via the word line voltage selection circuit 66. Note that, each word line WL gets to the active level (or inactive level) very slowly due to its parasitic capacitance and resistance.
As the selected word line is activated, the data stored in the memory cells connected thereto are read out onto the bit lines BLs to which the memory cells are connected respectively. At the same time, the data in the dummy cells connected to a dummy word line are drawn out onto the bit lines (not shown) that are complementary relative to the above bit lines BLs and to which the dummy cells are connected respectively. The difference between the electric potential of each of the bit lines BLs and that of the corresponding one of the complementary bit lines is sensed and amplified by the corresponding one of the sense amplifiers 69 (arranged corresponding to the respective pairs of the bit lines BLs and the complementary bit lines although they are shown as a single block 69 in FIG. 7). Meanwhile, there is a time lag, or delay, from the instant when the voltage of the selected word line rises to the time when the data stored in the memory cells MCs are read out onto the bit lines BLs. To compensate the delay, the word line delay compensation circuit 65 transmits to the sense amplifier drive circuit 68 a sense amplifier control signal SEN that is compensated for the delay and the sense amplifier drive circuit 68 supplies the sense amplifier 69 with a sense amplifier activation signal SAN, SAP according to the control signal SEN. The electric potential of the bit lines and that of the complementary bit lines of the above bit line pairs are set to level "H" and level "L" respectively by the output of the sense amplifiers to refresh the memory cells connected to the selected word line.
Then, as a column address strobe signal CAS externally supplied to the CAS input circuit 71 is activated and goes to level "L", all the column-related circuits start operating. Under this condition, the column decoder 75 selects a column or a bit line according to the signal obtained by decoding the column address signal. Then, the output (read out data) of the sense amplifier corresponding to the selected column are drawn onto a data line DQ (not shown). Thereafter, as the RAS signal and the CAS signal are turned back to the inactive level ("H"), the selected word line also goes back to the inactive level ("L") and the electric potentials of the bit line pairs and those of the input/output node pairs of the sense amplifiers connected thereto respectively are equalized.
As for writing data, a write enable signal WE is turned to the active level ("L") while a selected word line and the related sense amplifiers are activated. Consequently, the data to be written are stored in the sense amplifier for the selected column via a data lines DQ. Thereafter, the RAS signal and the CAS signal are turned back to the inactive level ("L") to complete a cycle of operation of writing data into the memory cells.
With the above conventional technique of accessing a memory cell, the selected word line is held to the active level all the time from the instant when a supplied RAS signal is turned to the active level to the instant when it is turned back to the inactive level and the time is considerably long. More specifically, since the selected word line is held to the active level (or a word line driving stepped-up voltage is applied to the gates of the memory cells of the selected row) for a long time, a high electric field strength come to be applied to the gate oxide films of the NMOS transistors of the memory cells of the selected row to eventually reduce the reliability of the memory cells.
Additionally, during the time when the selected word line is held to the active level, the word line driving stepped-up voltage falls gradually because of the leak current of the transistors of the transfer blocks of the word lines of all the unselected rows and that of the PN junctions. This fact provides another problem when a RAS signal is activated for a long time. In order for a RAS signal to be activated for a long time nevertheless, the leak current compensation circuit 76 has to be arranged on the output side of the word line drive voltage source 64 to consequently increase the overall patterned area and the electric power consumption of the device.
Still additionally, for a data reading operation, the electric potentials of the bit line pairs and those of the corresponding input/output node pairs of the sense amplifiers connected thereto are equalized after the RAS signal is turned back from the active level to the inactive level so that a prolonged period of time is required to restore the electric potentials for another data reading operation (or precharge the bit line pairs and the input/output node pairs for another reading operation).
Finally, for writing data at the completely "H" or "L" level into a memory cell in a data writing operation, the selected word line has to be completely turned back to the inactive level as a result of the level shift of the RAS signal from the active level to the inactive level before the electric potentials of the bit line pairs and the corresponding input/output node pairs of the sense amplifiers connected thereto are equalized so that a prolonged cycle time is required for a data writing operation.
In short, the selected word line of a conventional DRAM is required to stay at the active level for a prolonged period of time and a high electric field strength come to be applied to the gate oxide films of the NMOS transistors of the memory cells of the selected row to eventually degrade the gate oxide films and reduce the reliability of the memory cells. Additionally, the provision of a leak compensation circuit for the prevention of a fall of the level of the word line driving stepped-up voltage significantly increases the overall patterned area and the electric power consumption of the device.
Furthermore, since the electric potentials of the bit line pairs and those of the corresponding input/output node pairs of the sense amplifiers connected thereto are equalized only after the RAS signal is turned back from the active level to the inactive level, a prolonged period of time is required to restore the electric potentials for a data reading operation and also a prolonged cycle time is consumed for a data writing operation.